Events

We are conducting one month ONLINE Industrial approach Internship based Training and Project on DIGITAL SYSTEM DESIGN USING VERILOG AND SYSTEM VERILOG on EDA PLAYGROUND exclusive online practical lab based approach training to BE - ECE / TCE BRANCH, MTech Students to understand the tool, concept and technology ...

What you learn :

( see the link for detailed syllabus)

• Verilog for RTL Coding and Synthesis
• Adders, Finite State Machine, Memories
• System Verilog for RTL Coding and Synthesis
• Verilog / System Verilog Project :RTL Coding and Synthesis

Date Schedule :

Batch Starts on 12th Aug 2020
Weekly Three days of 2hrs each, Four Weeks
Timing: Evening 6pm to 8pm.