Jointly Organising Free Webinar on
for VLSI faculties and HODs of ECE / TCE / EIE and MTECH Coordinators.
This Webinar will help faculties to get upgrade on Market, Concept, Technology Trend, and also to upgrade the Curriculum and Tools.
Interested VLSI teaching faculties and HODs can participate with prior registration.
We will send the webinar link to those Registered Faculties on
23rd July 2020.
First Speaker: Mr.Ravi Shankar R, CEO, WhizChip Design Technologies Pvt. Ltd., Bengaluru.
Mr.Ravi is a technologist with a proven track record of about 25 years with leadership roles in ASIC design & verification, VLSI design methodologies, EDA and software development.
Second Speaker: Mr.Rakesh Agarwal, Country Manager, Lattice Semiconductor inc., India
Versatile experience in the field of FPGA-CPLD as application engineer, product engineer, Product manager and now to the top position in India. Having good network with most of the FPGA or programmable device companies in Asia Pacific countries.
Date: 25th July 2020
Time:10am to 12.30pm
This Webinar will help faculties to get upgrade on Market, Concept, Technology Trend, and also to upgrade the Curriculum and Tools.
Dr.Binoy Mathew, Director
Centralised Placement Cell - VTU
9448622548
SILICON MICROSYSTEMS & XIMAX SKILL UNIVERSITY,
BENGALURU
JAYACHANDRA ARADHYA.M.S
aradhya@simsindia.net
9844040444